1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming lateral and vertical FinFET devices and the resulting integrated circuit product.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
As it relates to FinFET devices, there are so-called lateral FinFET devices and vertical FinFET devices, the basic structure of which is well known to those skilled in the art. In general, when viewing a lateral FinFET device from above, the source/drain regions are positioned on opposite sides of the gate structure of the device. In contrast, when viewing a vertical FinFET device from above, the channel region of the device is positioned vertically below one of the source/drain regions while the other source/drain region is positioned vertically below the channel region, i.e., the channel region is positioned vertically between a lower source/drain region and an upper source/drain region. Unlike a lateral FinFET device, a vertical FinFET device is not symmetrical with respect to how it may be wired in the integrated circuit. That is, the electrical characteristics of a vertical FinFET device are different depending upon the direction of current flow, i.e., top-to-bottom or bottom-to-top. Thus, the use of traditional non-symmetric vertical FinFET devices limits design flexibility. In some applications, it is desirable to form both lateral FinFET devices and vertical FinFET devices on the same integrated circuit product. However, a process flow must be developed for forming both types of FinFET devices that is efficient and may be incorporated in a mass production manufacturing environment.
The present disclosure is directed to methods of forming lateral and vertical FinFET devices and the resulting integrated circuit product that may solve or reduce one or more of the problems identified above.